Today’s car is evolving from a machine that takes simple instructions from a human driver to an increasingly sophisticated computing platform that senses, thinks and acts autonomously. Traditionally, vehicle control systems responded directly to a driver’s commands. In autonomous systems by contrast, it is the car that gives those commands and then must execute them flawlessly to guarantee safety in all conditions. This need for safe guaranteed control has driven a rapid growth in demand for high-performance, safe computing solutions to control the “start, stop and steer” functions fundamental to all mobility.
“We see that the shift to next-generation autonomous and electric vehicles is introducing huge challenges to carmakers,” said Ian Riches, executive director in the Strategy Analytics Global Automotive Practice. “Not least of these is the ability to get silicon in hand fast enough and with enough performance headroom to ease the transitions to autonomous and advanced HEV/EV. A car can be extremely intelligent, but if it can’t act safely on a decision, you don’t have a reliable autonomous system at all.”
NXP has met the needs of carmakers developing future autonomous and hybrid electric vehicles with a newly available 800MHz microprocessor/microcontroller. The first of the new S32 product lines, the S32S microprocessors offer the highest performance ASIL D capability available today.2
The NXP S32S processors use an array of the new Arm Cortex-R52 cores, which integrate the highest level of safety features of any Arm processor. The array offers four fully independent ASIL D capable processing paths to support parallel safe computing. In addition, the S32S architecture supports a new “fail availability” capability allowing the device to continue to operate after detecting and isolating a failure – a critical capability for future autonomous applications.
NXP has partnered with OpenSynergy to develop a fully featured, real-time hypervisor supporting the NXP S32S products. OpenSynergy’s COQOS Micro SDK is one of the first hypervisor platforms that takes advantage of the Arm Cortex-R52’s special hardware features. It enables the integration of multiple real-time operating systems onto microcontrollers requiring high levels of safety (up to ISO26262 ASIL D). Multiple vendor independent OS/stacks can also run on a single microcontroller. COQOS Micro SDK provides secure, safe and fast context switching ahead of today’s software-only solutions in traditional microcontrollers.
Additional S32S Features and Benefits
The NXP S32 platform is the world’s first fully-scalable automotive computing architecture. Adopted by both premium and volume automotive brands, it offers a unified architecture of microcontrollers/microprocessors (MCU/MPU) and an identical software environment that can reduce development effort and maximizing software reuse across products and applications. The NXP S32 architecture addresses the challenges of future car development with a host of architectural innovations designed to allow carmakers to bring rich in-vehicle experiences and automated driving functions to market much faster than before.
“When we started the development of the S32S it was clear that just building another incremental microcontroller was not what customers needed to handle the safety and performance requirements of next-generation and autonomous vehicles,” said Ray Cornyn, vice president of Vehicle Dynamics and Safety. “Our new safety processors leverage the high performance multi-core benefits of the S32 Arm platform while still supporting traditional microcontroller ease of use and environmental robustness.”
S32S will be sampling in Q4 2018 to NXP’s Automotive Alpha customers. Contact your sales person for more information.
1 Source: Strategy Analytics 2017
2 Performance statement based on publicly available information
About NXP Semiconductors
For more information, please contact:
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Kiyomi Masuda (増田 清美)
A photo accompanying this announcement is available at http://www.globenewswire.com/NewsRoom/AttachmentNg/f25b1034-d40a-410c-87eb-bb3f4ee096b6
June 18, 2018 at 2:00 AM EDT
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