Multi-Layered Approach to Embedded Systems Security
Building on the company's security expertise, NXP brings multi-layered, hardware-enabled protection scheme that is unique in the industry today. Vital to physical and run-time protection, this layered security approach protects embedded systems with:
These features in conjunction with Arm® Cortex-M33 enhancements of Arm TrustZone® technology for Armv8-M architecture and Memory Protection Unit (MPU), ensures physical and runtime protection with hardware-based, memory mapped isolation for privilege-based access to resources and data.
"The promise of the connected world through the
Unique Security Enhancements
A cornerstone to establishing device trustworthiness is NXP's ROM-based secure boot process that utilizes device-unique keys to create an immutable hardware ‘root-of-trust'. The keys can now be locally generated on-demand by an
Furthermore, NXP's SEE improves the symmetric and asymmetric cryptography for edge-to-edge, and cloud-to-edge communication by generating device-unique secret keys through innovative usage of the SRAM PUF. The security for public key infrastructure (PKI) or asymmetric encryption is enhanced through the Device Identity Composition Engine (DICE) security standard as defined by the
"Maintaining the explosive growth of connected devices requires increased user trust in those devices," said
Accelerating Machine Learning and DSP Compute Performance
NXP strategically selected Cortex-M33 to leverage the first full-feature implementation of Armv8-M architecture to provide security platform benefits and substantial performance improvements compared to existing Cortex-M3/M0 MCUs (over 15 to 65 percent improvement, respectively). One of the key features of the Cortex-M33 is the dedicated co-processor interface that extends the processing capability of the CPU by allowing efficient integration of tightly-coupled co-processors while maintaining full ecosystem and toolchain compatibility. NXP has utilized this capability to implement a co-processor for accelerating key ML and DSP functions, such as, convolution, correlation, matrix operations, transfer functions, and filtering; enhancing performance by as much as 10x compared to executing on Cortex-M33. The co-processor further leverages the popular CMSIS-DSP library calls (API) to simplify customer code portability.
LPC5500 Platform – Multi-core Cortex-M33 MCUs for Industrial & IoT Applications
Single- or Dual-core Cortex-M33 with integrated DC-DC delivers industry-leading performance at a fraction of power budget, of up to 90 CoreMarks™/mA. The high density of on-chip memory, up to 640KB flash and 320KB
i.MX RT600 Crossover Platform – Power-Optimized Cortex-M33 / DSP MCUs for Real-Time Machine Learning (ML) / Artificial Intelligence (AI) Applications
Wide operating voltage and performance range, with up to 300MHz Cortex-M33, up to 600MHz Cadence® Tensilica® HiFi 4 DSP and shared on-chip
Dover CoreGuard – Security with Hardware-Based Defense
NXP has partnered with Dover Microsystems to introduce Dover's CoreGuard™ technology in future platforms. CoreGuard is a hardware-based active defense security IP that instantly blocks instructions that violate pre-established security rules, enabling embedded processors to defend themselves against software vulnerabilities and network-based attacks. For more information, click here.
NXP at Upcoming Shows and Conferences
NXP plans to demonstrate its latest edge compute offerings at Arm TechCon this week in Booth #620. Also, NXP plans to demonstrate its industrial IoT solutions for ML at IoT World Barcelona this week in Booth #261 located in the Gran Via – Hall 2, Street B, Level 0.
NXP and the NXP logo are trademarks of
For more information, please contact:
|Americas||Europe||Greater China / Asia|
|Tate Tran||Martijn van der Linden||Esther Chang|
|Tel: +1 408-802-0602||Tel: +31 6 10914896||Tel: +886 2 8170 9990|
|Email:email@example.com||Email: firstname.lastname@example.org||Email: email@example.com|
October 10, 2018 at 9:01 AM EDT
|Receive News Alerts|